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Sandy Bridge, PCIe Gen 3 Give Tibco's FTL a Boost

Intel's recently introduced Sandy Bridge microchips, together with the latest PCI Gen 3 interconnect technology, is giving a performance boost to Tibco Software's FTL messaging middleware - for both intra-server and inter-server communications.

Officially known as the Xeon Processsor E5-2600 family, Sandy Bridge incorporate up to eight cores and 20 MB of cache, with integrated PCIe interconnects and multiple RAM memory paths.

According to Tibco's senior product architect for messaging Bill McLane, Sandy Bridge boosts FTL performance significantly, compared to Intel's previous Westmere architecture chips. For intra-server (shared memory) communications, typical performance is increased from around 490 nanoseconds to 400. And for inter-server, using InfiniBand and RMDA, the speed up is from 3.4 microseconds to 2.25.

McLane attributes the performance improvements to the improved CPU architecture, the integration of the latest PCI Gen 3 on the motherboard, and Mellanox Technologies' support for Gen 3 in its networking interfaces. He also adds that jitter has been significantly reduced.

View a webinar recording on FTL's latest peformance here.

The latest version of FTL - 2.0.1 - adds support for wide area connectivity between different network domains - for example bridging RDMA-based networks in different locations via a TCP/IP wide area link.

Part of this support is that content filtering in 2.0.1 is now performed at different points in the network architecture depending on the network transport. For example, for multicast, filtering continues to be performed at the consumer. But for TCP/IP, the filtering takes place at the publisher, thus reducing network traffic.


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